As is well known, today's technology allows so-called multi-level memory cells, that is memory cells whose threshold voltage can be programmed at any of several predetermined levels, to be produced.
EPROM, EEPROM, and Flash cells can be programmed by fine control of the charge injected into the floating gate so as to provide devices having different threshold voltages.
A non-volatile memory cell programmable at m=2.sup.n threshold levels can store n bits. A non-volatile memory cell having four threshold voltages, for example, can store two bits, and a cell with sixteen different threshold values can store up to four bits.
Thus, for a given silicon area (the memory cell matrix, or array, forming a major portion of a non-volatile memory), a device comprising multi-level memory cells would contain, in the above examples, two or four times as much information as is contained in devices comprising conventional cells, i.e., two-level cells.
A most promising technique for programming multi-level non-volatile memory cells is known as the PV (Program & Verify) technique, which is also employed with two-level non-volatile memory cells and Flash memories, e.g., for soft-programming "erratic" bits.
This technique consists of applying suitable voltages to the terminals of a memory cell during its programming, and subsequently reading its information contents during the verification ("verify") phase.
The verify operation consists of reading the state of the cell (e.g., the current flowing through the cell under predetermined bias conditions, or the voltage developed thereby on a suitable load), and subsequently comparing it with a suitable reference known as the "PV" reference.
The selected cell is programmed by applying successive program pulses to both the control gate and drain terminals of the memory cell. The analog voltage applied to the gate terminal of the cell is generated internally by a dedicated circuit.
The program gate voltage (referred to as Vpr hereinafter) could be different from the program supply voltage Vpp, set to 12 V during the program and verify operation.
The appropriate voltages are applied to the word-lines through the driving stages of the corresponding row decoding circuit.
In a memory architecture of the NOR EPROM type, all the drivers have the supply voltage terminal in common, since no segmenting (i.e., no organizing of the memory into sectors) is provided. Therefore, the capacitive load, as seen from that node, is found to be quite significant where multi-megabit memories are involved, which makes current solutions for applying the program voltage generated internally in the memory chip impracticable due to the long switching time required for the transitions between "program" and "verify" phases.
Since multi-level memories require a large number of program pulses, it is necessary for these switching times to be the shortest possible.
FIG. 1 shows a conventional row decoding architecture as commonly employed in a number of standard non-volatile memory devices. An address entered from the outside is decoded using a tree structure, so as to minimize the number of inputs to the internal logic gates and optimize the so-called decoding structure pitch to match the pitch of the matrix cells.
Some so-called pre-encode signals are generated to decode the desired word line, which are then utilized as select inputs to a final row selector (second-level decoding). The general decoding circuit comprises a low-voltage logic (being supplied Vdd) and a word line (Vpc) driver for the application of appropriate voltages to the selected word line, and the appropriate non-selection of "unselected" rows. Of course, the specific structure of a decoding network would be dependent on the type of the memory device architecture. For example, with logic NOR architectures, the selected word line would be set to a predetermined voltage according to the operation to be executed, typically to a suitable high voltage Vpr in the programming phase and to a suitable lower voltage during the read and verify phases (for example, to the supply voltage Vdd (3 or 5 V) in the read mode).
The unselected rows are disabled by the application of a low voltage, typically a ground potential, to the respective word-lines. The function of the row driver is to transfer the required voltage to the corresponding word line, according to the address selected and the operational phase. FIG. 2 shows the typical structure of a row driver as currently employed in memory architectures of the NOR type. The driver consists of an inverter which is supplied a voltage Vpc and has an input IN connected to the output of a selection logic whose logic levels are 0 V for L (Low), and Vdd=3 or 5 V for H (High).
A pull-up PMOS transistor M1 is connected between IN and Vpc. If the corresponding row is selected (IN=L or 0 V), the output OUT goes to the value of the voltage Vpc. In this case, the transistor M1 would be `on` and a sinking of static power would occur. In fact, there is a current flowing, between Vpc and ground via M1, through the pull-down branch of the second decoding stage.
If the row is not selected (IN=H, i.e., no conductive path is provided between IN and ground through the pull-down branch of the second decoding stage), OUT is at 0 V. To provide an output OUT=0 V, transistor M2 must be turned off completely and transistor M3 turned on, these transistors forming parts of the circuit shown in FIG. 2. For this reason the pull-up transistor M1 is arranged to ensure, by its suitably selected resistive value, that the voltage IN will follow the voltage Vpc, and that OUT is 0 V.
With CMOS technologies of the dual metal level type, on the other hand, the driver structure may be as shown diagramatically in FIG. 3, wherein the gate terminal of M1 is connected to the output OUT directly. This expedient, besides ensuring full operation for the structure, allows the sinking of static power typical of the first structure when IN=L, and therefore OUT=H, to be eliminated. The first structure is useful essentially with single metal level technologies, where restrictions on the layout (in particular, compliance with the pitch of the memory array) make connecting the gate of M1 to the output OUT very difficult or even impossible.
In either case, the driver structure involves the use of a single voltage supply Vpc for both the inverter and M1. In a multi-level or "multi-megabit" memory, the capacitive load as seen from that node would be too high, especially where no organization into sectors of the memory architecture is provided, for example, for a 4 Mcells memory comprising 4096 rows and not organized into sectors, the overall load would be approximately 800 pF with conventional fabrication technology, when all the parasitic contributions are taken into account.
This value is of minor importance in the instance of standard two-level memories, wherein no fast switching between the program and verify phases is required, because the number of PV operations, and consequently the number of PV switchings, is small. However, this value would hinder the use of the circuit structures shown in multi-level memories which are programmed by the application of several pulses of the program voltage to the gate terminal of a selected cell. In this case, fast switching between the application phase of the high program voltage and the verification phase becomes necessary in order to keep the overall cell programming time within limits.
For example, the required switching time may be on the order of 100 ns where each program/verify pulse duration is about 1 .mu.s. These capacitance and time values require particular performance of both the program voltage generator and the internal read voltage generator. In fact, a dynamic current of approximately 50 mA would be needed for proper charging/discharging of the node Vpc during program/verify switchings.
A possible solution to the problem could be that of segmenting the memory array and the decoding circuitry. For example, a selector could be connected between the supply terminals of the final stages (i.e., of the drive stages of the decoding circuitry) and the voltage supply line. The driving stages are grouped into different groups, where all the driving stages of the same group have the respective supply terminal short-circuited and are therefore supplied through the same selector. In operation, only the selector corresponding to the selected driving stage is activated, and therefore only the driving stages in the selected group constitute a real capacitive load for the supply voltage Vpc. On the one side, this possibility would reduce the overall load as seen from Vpc, but this would be obtained at the expense of increased complexity for the decoding circuit, with its attendant disadvantages (increased complexity of decoding management, increased area occupation, etc.). This solution, moreover, would be applicable to Flash memories, which are organized into sectors, but not to EPROMs, whose architectures are not organized into sectors by definition.